Wafer bump in the face of lead-free solder and fine pitch challenge
2016/3/6 view:
Lead in the electronics industry has a very wide range of application requirements, this is because it is relatively inexpensive, and has a good conductivity and relatively low melting point. However, according to the provisions of RoHS and other instructions, to eliminate the use of harmful materials in electronic products. As a result, people are constantly looking for alternatives to lead.
At present, the Packaging WLP (Wafer-Level) is a very small part of the global WLP, which is based on the micro pitch lead-free solder. Now there is little demand for less than 100 m bump pitch (a convex center to another convex center distance), the semiconductor technology roadmap for Semiconductors (ITRS) is expected in 2009 will have a bump wafer manufacturers need to use 100 m bump pitch. For example, IBM, a grandfather grade company that produces solder bumps, still uses its C4 bump technology on many of the products, with a pitch of 220 M. Little demand but development is very rapid application is in the interconnection of very fine, such as high density image detector array (pixelated detector arrays).
It is estimated that 30% of all solder joints in electronic packaging products are used for passive devices. The Micro Devices California and AVX company introduced a passive bump on a wafer that uses a "integrated passive device" way to manufacture. They are used in the thick Ti/Cu bump below the metal spray plating (metallization under-bump, referred to as UBM) technology, while the use of lead and lead-free solder. A lead or lead free solder ball with a size of 150 to 300 m is used on the wafer to be placed on the top of a passive device, which can be used as a formal WLP.
Wafer level bump formation
Injection in wafer level to achieve several basic methods of bump solder paste stencil printing, solder, solder ball placement and solder fine plating. Solder spray, ball placement, and embedded bumps are the methods of manufacturing the subsequent development of the convex points, which can provide a high degree of design flexibility, but require a longer period. The latest photographic tool does not need to be designed to change, it can meet the needs of solder spray WLP. Using CAD software of the device can be a flexible adjustment of the program, so that can quickly meet the new requirements of the solder joints. American PAC tech and MicroFab technologies through the practice proved that using their precision equipment can be carried out quickly solder jetting, thereby forming a convex point; UBM method generally used is Ti / Cu and in aluminium materials of nickel gold plating (electroless the nickel gold. (ENIG). At the same time, the use of prefabricated solder ball placement methods are generally subjected to relatively large size, and in the face of the new design requires as little as possible tool changes, stencil printing, fine plating coating and indium evaporation technique can provide the highest density of gap size.
High density image detection
A rapidly growing field is an array of images with a high density of image pixels in the field to meet the requirements of a wide variety of detection applications. These arrays are sometimes required per square centimeter to 40 000 pixels, each pixel requires the use of a solder bump, connect the silicon chip detector and readout IC, here dissolve the all silicon process technology. In such a small area, there is such a high density of connections, is required in these systems with no more than 50 m spacing of the main reasons. There are two design schemes of the fine pitch has started implementation: one is using lead in solder, such as electroplating eutectic SnPb alloy, in order to achieve the spacing of 25 to 50 mu m; another method is using indium solder, the spacing of 15 to 50 mu m can be achieved.
In Europe, researchers published the use of indium bump technology in the WLP above to achieve a 15 m distance message, the technology for imaging infrared focal plane array system (IR focal plane array systems pixelated). Indium bump is a simple process technology, it can be obtained as long as there is little research power, the fact that the challenge is to prove that the distance between 50 m. However, in general, during the implementation of the assembly process, because of its very low shear strength, the yield will be very low. Therefore, SnPb with high strength can meet the needs of the majority of high energy physics researchers to use image detector array to carry out the research of micro particles.
The international organization also requires the use of high density image detectors to meet the needs of a wide range of applications, such as astrophysics, medical images and protein crystallization research, etc.. At present, the application of high density image detectors has not been forced to use lead-free solder. However, with the continuous expansion of market of medical image, the solder interconnection requirements also increasing, so it is increasingly politicians and environmentalists are concerned, this will also push towards the use of lead-free solder. In order to far away from the high density of lead in solders, researchers provide a use 3D silicon interconnection scheme. In this scheme used a copper through-hole technology, so as to coexist in harmony with the environment welding materials found a suitable location.
Application of large scale lead-free solder。
At present, the Packaging WLP (Wafer-Level) is a very small part of the global WLP, which is based on the micro pitch lead-free solder. Now there is little demand for less than 100 m bump pitch (a convex center to another convex center distance), the semiconductor technology roadmap for Semiconductors (ITRS) is expected in 2009 will have a bump wafer manufacturers need to use 100 m bump pitch. For example, IBM, a grandfather grade company that produces solder bumps, still uses its C4 bump technology on many of the products, with a pitch of 220 M. Little demand but development is very rapid application is in the interconnection of very fine, such as high density image detector array (pixelated detector arrays).
It is estimated that 30% of all solder joints in electronic packaging products are used for passive devices. The Micro Devices California and AVX company introduced a passive bump on a wafer that uses a "integrated passive device" way to manufacture. They are used in the thick Ti/Cu bump below the metal spray plating (metallization under-bump, referred to as UBM) technology, while the use of lead and lead-free solder. A lead or lead free solder ball with a size of 150 to 300 m is used on the wafer to be placed on the top of a passive device, which can be used as a formal WLP.
Wafer level bump formation
Injection in wafer level to achieve several basic methods of bump solder paste stencil printing, solder, solder ball placement and solder fine plating. Solder spray, ball placement, and embedded bumps are the methods of manufacturing the subsequent development of the convex points, which can provide a high degree of design flexibility, but require a longer period. The latest photographic tool does not need to be designed to change, it can meet the needs of solder spray WLP. Using CAD software of the device can be a flexible adjustment of the program, so that can quickly meet the new requirements of the solder joints. American PAC tech and MicroFab technologies through the practice proved that using their precision equipment can be carried out quickly solder jetting, thereby forming a convex point; UBM method generally used is Ti / Cu and in aluminium materials of nickel gold plating (electroless the nickel gold. (ENIG). At the same time, the use of prefabricated solder ball placement methods are generally subjected to relatively large size, and in the face of the new design requires as little as possible tool changes, stencil printing, fine plating coating and indium evaporation technique can provide the highest density of gap size.
High density image detection
A rapidly growing field is an array of images with a high density of image pixels in the field to meet the requirements of a wide variety of detection applications. These arrays are sometimes required per square centimeter to 40 000 pixels, each pixel requires the use of a solder bump, connect the silicon chip detector and readout IC, here dissolve the all silicon process technology. In such a small area, there is such a high density of connections, is required in these systems with no more than 50 m spacing of the main reasons. There are two design schemes of the fine pitch has started implementation: one is using lead in solder, such as electroplating eutectic SnPb alloy, in order to achieve the spacing of 25 to 50 mu m; another method is using indium solder, the spacing of 15 to 50 mu m can be achieved.
In Europe, researchers published the use of indium bump technology in the WLP above to achieve a 15 m distance message, the technology for imaging infrared focal plane array system (IR focal plane array systems pixelated). Indium bump is a simple process technology, it can be obtained as long as there is little research power, the fact that the challenge is to prove that the distance between 50 m. However, in general, during the implementation of the assembly process, because of its very low shear strength, the yield will be very low. Therefore, SnPb with high strength can meet the needs of the majority of high energy physics researchers to use image detector array to carry out the research of micro particles.
The international organization also requires the use of high density image detectors to meet the needs of a wide range of applications, such as astrophysics, medical images and protein crystallization research, etc.. At present, the application of high density image detectors has not been forced to use lead-free solder. However, with the continuous expansion of market of medical image, the solder interconnection requirements also increasing, so it is increasingly politicians and environmentalists are concerned, this will also push towards the use of lead-free solder. In order to far away from the high density of lead in solders, researchers provide a use 3D silicon interconnection scheme. In this scheme used a copper through-hole technology, so as to coexist in harmony with the environment welding materials found a suitable location.
Application of large scale lead-free solder。
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